1. Field of the Invention
The present invention is a continuation-in-part (CIP) of U.S. patent application Ser. No. 09/298,964. It generally relates to a method of forming MOSFETs in an integrated circuit (IC), and more particularly, to a method of forming a poly gate and a polycide gate with an equal height on one chip.
2. Description of the Prior Art
The present invention is a continuation-in-part (CIP) of U.S. Pat. application Ser. No. 09/298,964. Integrating the periphery circuits on a chip is a stream of electronic products in the technology development of the electronic industry. Recently, the improvement of semiconductor processing has made the integration of memory cells and periphery circuits on one chip possible.
Taking an image device as an example, in order to improve the performance and resolution of images, each image has to be divided into millions of pixels. Then each pixel is stored in a memory cell in the form of digital data. One aspect to show the characteristics of an image device is the accuracy of electronic signals stored in memory cells for each pixel array. If the problem of current leakage occurs in the memory cells, the electronic signals of pixels cannot be recorded exactly which will produce many dots on the image. Another aspect to show the characteristics of an image device is the accessing speed of the periphery circuits integrated on the chip. The accessing speed has to be fast enough for dealing with a great amount of data. Therefore, for an image device a chip should correspond to two demands concurrently. One of the demands is that current leaking is rigidly limited, but the accessing speed is not important. Another demand is that a high accessing speed is necessary, but the current leaking is not the key consideration.
In a semiconductor device, a metal-oxide-semiconductor field-effect transistor (MOSFET) is one of the most important elements for the VLSI integrated circuits. A MOSFET includes a gate structure, a source and a drain, wherein the source and drain are located at the sides of the gate structure. The gate structure includes a metal layer at the top referred to as gate electrode, an oxide layer under the metal layer referred to as gate oxide, and a semiconductor layer at the bottom.
Typically, the metal layer at the top of the gate structure is formed of poly-silicon, thereby the gate structure is referred to as poly gate. Because poly-silicon does not have a lowest resistance, sometimes a layer of suicide is deposited overlying the poly-silicon layer to form a polycide gate for lowering the resistance.
Because poly gate does not have a lowest resistance, its accessing speed is not the fastest. But the problem of current leaking in poly gate is not serious, which makes poly gate be a good element for the pixel array area in an image device. On the other hand, the problem of current leaking in polycide gate is worse than that in poly gate, but polycide gate has a lower resistance, which can decrease the TC time delay and increase the device switching speed. Therefore, the polycide gate is better than poly gate to be the element for the periphery circuit area in an image device for providing a high speed to deal with a great amount of pixel data in the periphery circuit area.
In order to form poly gate and polysice gate on one silicon substrate concurrently, several issues about the process and products are derived. Referring now to FIG. 1, a cross-sectional view of the poly gate and polycide gate formed on a substrate according to a prior art of the present invention, a gate oxide layer 2 is formed on a semiconductor substrate 1. Then, a poly gate including a poly-silicon layer 3 is formed at the poly gate area by the methods of deposition, photolithography and etching. Next, a polycide gate is formed at the polycide gate area, wherein the polycide gate has a poly-silicon layer 3 and a silicide layer 4.
Because poly-silicon has a higher resistance than polycide, and the height of poly gate is lower than the height of polycide gate, as shown in FIG. 1, the conventional structure in FIG. 1 makes the poly gate have a much higher sheet resistance than the polycide gate. Therefore, the accessing speed of the products produced by the conventional technology is not good enough. For the image device described above, the obvious difference of accessing speed between the cell area and the periphery area cannot make the device achieve a best operating state. Therefore, the present invention seeks to provide a method for solving this problem.
It is an object of the present invention to provide a method of forming a poly gate and a polycide gate with an equal height in a semiconductor device fabricated on a substrate to reduce the sheet resistance of the poly gate electrode.
In order to achieve the foregoing object, the present invention provides a method of forming a poly gate and a polycide gate with an equal height in a semiconductor device fabricated on a substrate, comprising the steps of forming a gate oxide layer on a substrate; sequentially depositing a first poly-silicon layer, a silicide layer, and a capped dielectric layer; patterning a polycide gate by using a first photo-resist layer, and then etching the capped dielectric layer and the silcide layer; removing the first photo-resist layer; forming spacers on the sidewall of the silicide layer; depositing a second poly-silicon layer; patterning a poly gate by using a second photo-resist layer, and etching the first poly-silicon layer and the second poly-silicon layer; and finally removing the second photo-resist layer.
Alternatively, the present invention provides another method of forming a poly gate and a polycide gate with an equal height in a semiconductor device fabricated on a substrate, comprising the steps of forming a gate oxide layer on a substrate; sequentially depositing a poly-silicon layer and a capped dielectric layer; patterning a polycide gate by using a first photo-resist layer, and then etching the capped dielectric layer and a portion of the poly-silicon layer having a certain thickness; removing the first photo-resist layer; performing thermal oxidation on the poly-silicon layer so as to form a silicon oxide layer on the poly-silicon layer, forming spacers on the sidewall of the poly-silicon layer; depositing a silicide layer; patterning a poly gate by using a second photo-resist layer, and etching the silicide layer; anisotropically etching the poly-silicon layer; and finally removing the second photo-resist layer.